1. Field of the Invention
The present invention relates to a package for a semiconductor device, and more particularly to a wire arrayed chip size package and a fabrication method thereof, which are small and thinly packaged so that the package has a similar size with a semiconductor chip.
2. Description of the Conventional Art
A general structure of a conventional chip size package consists of metal pattern units ribbon-bonded to chip pads of a semiconductor chip, solder balls attached on the metal pattern unit and a molding resin sealing peripheral portions of the chip pads, wherein electrical signals of the chip pads are externally transmitted through the solder balls.
FIG. 1 illustrates the cross-section of a structure of the above-mentioned conventional chip size package. Referring to FIG. 1, a method of fabricating the conventional chip size package will also be discussed.
Next, nickel and gold plating are sequentially applied on the surfaces of the metal pattern units 14 which are exposed on the holes 13 in order to perform the ribbon bonding 19 to chip pads 18. A semiconductor chip 10 is attached to a bottom surface of the insulating film tape 12. Then the ribbon bonding 19 is performed at a portion formed between the chip pads 18 and the corresponding metal pattern units 14 through the holes 13. A molding process is then performed by which an epoxy mold compound (EMC) 20 is injected into each of the holes 13.
Further, flux is applied on the portions of the metal pattern units 14, on which solder balls 22 will be attached, the solder balls 22 are mounted on the flux and then the solder balls 22 are fixed by reflowing. The fabrication method of the conventional chip size package is completed by singularizing the resultant package.
However, in the thusly fabricated conventional chip size package, since the solder balls 22 are used as external terminals which externally transmit electrical signals, it is required to have the metal pattern units 14 which transmit the electrical signals from the chip pads 18 to the solder balls 22 and also it is required to form a separate region for performing the ribbon bonding 19 of the metal pattern units 14 and the chip pads 18. In addition, in consideration of a size of each solder ball itself and a predetermined distance between the solder balls 22, there is a problem in which the number of pins provided in a package must be limited. Further, since the electric signal transmission is achieved from the chip pads 18 through various mediums such as the ribbon bonding 19, the metal pattern units 14 and the solder balls 22, it is difficult to improve the electric characteristics of the package. Lastly, since a back side of the semiconductor chip is externally exposed, it is difficult to protect the chip from external surroundings.
Accordingly, the present invention is directed to a wire arrayed chip size package and a fabrication method thereof which obviate the problems and disadvantages associated with the conventional art.
An object of the present invention is to provide a wire arrayed chip size package in which wires which are considerably finer than conventional solder balls are used as external terminals and wires are directly bonded between chip pads and metal pattern units, which results in achieving a size thereof similar to a semiconductor chip and high integration of pins in the same chip size.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a wire arrayed chip size package which includes: a semiconductor chip having a plurality of chip pads; an insulating film tape having a plurality of holes of which a bottom surface is attached with the semiconductor chip; metal pattern units formed on the insulating film tape; a solder mask covering the insulating film tape and portions of the metal pattern units; metal pattern unit-electroplates formed on portions of the metal pattern units which are not covered with the solder mask; wires electrically connecting the chip pads and the metal pattern unit-electroplates; and a molding resin for sealing side surfaces and a bottom surface of the semiconductor chip, excluding an upper surface thereof.
Also, to achieve the above object of the present invention, there is provided a method for fabricating a chip size package which includes: etching a copper film applied on an insulating film tape, except for longitudinal marginal portions of the copper film, metal pattern units thereof which are peripheral to portions corresponding to chip pads of a semiconductor chip and portions thereof connecting the longitudinal marginal portions and the metal pattern units; forming a solder mask on the insulating film tape excluding inner holes of the metal pattern units, the copper film excluding four edge portions of the longitudinal marginal portions thereof and exterior circular marginal portions of the metal pattern units; electroplating portions of surfaces of the metal pattern units on which the solder mask is not formed, for thereby forming metal pattern unit-electroplates; attaching the semiconductor chip to a bottom surface of the insulating film tape; molding side surfaces and a bottom surface of the semiconductor chip with an epoxy mold compound; etching portions of the insulating film tape formed on the chip pads for thereby exposing the chip pads; electrically connecting by wires the metal pattern unit-electrodes and the corresponding chip pads; and eliminating portions of the copper film remaining at the four edge portions of the longitudinal marginal portions thereof and cutting the resultant insulating film tape to be separated into individual units.